1. Field of the Invention
The present invention relates to an information transfer equipment, and in particular to an information transfer equipment which executes a monitoring control of a channel portion by transmitting/receiving monitoring control information between the channel portion and a common portion.
2. Description of the Related Art
In recent years, a communication system has aimed at a high transmission capacity and an enhanced monitoring control function regardless of its kind, resulting in an enlarged hardware scale. In a system accomplishing the monitoring control function, it is important that an information transfer equipment works efficiently on the aspects of function and cost.
Generally, an information transfer equipment mounts thereon a microprocessor (CPU) and performs its main function with firmware/software. In particular, a function block which manages a monitoring control has achieved a speedup and a high-performance in the form of multi-CPU.
Also, such an information transfer equipment enlarged in its hardware scale as mentioned above is generally composed of a plurality of racks. Accordingly, the monitoring control apparatus must execute the monitoring control to all of the racks.
Specifically, a high-capacity communication system is composed of a channel portion for processings per transmission line having a certain unit of capacity called a channel, and a common portion for receiving information from the channel portion and for transmitting information to the channel portion. Generally, a plurality of the channel portions are mounted on the system. Therefore, the system is to have a plurality of racks in case a plurality of channel portions are mounted thereon, so that it is general to perform data transmission by physically connecting each of the channel portions and the common portion with numerous cables.
For example, in a conventional monitoring control system of a communication system adapted to SDH (Synchronous Digital Hierarchy), monitoring control information is transmitted between each of the channel portions and the common portion as follows:
(1) CPU bus access signals between a CPU (common portion) performing the monitoring control of the system and the channel portions;
(2) Order wire signals;
(3) Data communication channel signals; and
(4) Radio protection switchover signals.
When signals such as the above-mentioned (1)-(4) are individually connected with leased cables, the competitiveness of the equipment is impaired in terms of size, cost, operational stability of the equipment, and the like. Therefore, the Japanese Patent Application No. 10-151620 by the inventors of the present invention is mentioned as a technology having an arrangement in which a synchronous communication path within the equipment is provided by integrating these signals, and the common portion and the channel portions are connected with a single system of a communication path for information transfer within the equipment.
In the information transfer equipment of the Japanese Patent Application No. 10-151620 (hereinafter, referred to as prior art information transfer equipment), as shown by a schematic arrangement in FIG .9, a multiplexer of a common portion 10 multiplexes and transmits, by broadcasting, monitoring control information 90 into a predetermined position of a Time Division Multiplexing (hereinafter abbreviated as TDM) frame. A demultiplexer of each of channel portions 50_1-50_7 receives the TDM frame and demultiplexes therefrom the monitoring control information 90.
Also, the multiplexer of the channel portions 50 multiplexes and transmits each of the monitoring control information 90_1-90_7, . . . (hereinafter, represented by a reference numeral “90”) into a Time Division Multiple Access (hereinafter abbreviated as TDMA) frame based on a channel number preset for its own. A demultiplexer of the common portion 10 receives the TDMA frame and demultiplexes therefrom the monitoring control information 90.
Namely, the common portion 10 executes the TDM-multiplexing of plural kinds of the monitoring control information 90 on a transmission line 110 of one system and broadcasts it to the channel portions 50. Each of the channel portions 50 executes the TDMA-multiplexing of the monitoring control information 90 of its own on the reception line 111 of one system and transmits it to the common portion 10.
As a result, it becomes possible to connect the common portion 10 to the channel portions 50 with the information transfer equipment in which an interface is integrated to one system.
Hereinafter, the arrangement and the operation of the common portion 10 in the prior art information transfer equipment will be described referring to FIG .10.
The common portion 10 is provided with OW interfaces 21_1-21_i (hereinafter, represented by a reference numeral “21”), DCC interfaces 22_1-22_j (hereinafter represented by a reference numeral “22”), an RPS interface memory 23, and a CPU interface 11 respectively connected to an OW processor and a DCC processor (no reference numeral shown for both), an RPS LGC processor 20, and a CPU 1.
A write address data packet generator 12, a read controller 15, and a CPU read interface memory 16 are connected to the interface 11.
Also, CPU write packet buffers 13_1-13_k (hereinafter, represented by a reference numeral “13”) are commonly connected to the packet generator 12. The packet buffer 13, the interfaces 21, 22, and the memory 23 are commonly connected to an input terminal of a multiplexer 45 along with a channel-specific (by-channel) transmission synchronous controller 44 and a multi-frame generator 46. An output terminal of the multiplexer 45 is connected to an interface processor 41, which is connected to transmission lines 110, 111 on the output and the input sides. The processor 41 is also connected to a demultiplexer 42, which is commonly connected to the interfaces 21, 22, the memory 23, the memory 16, and a channel-specific status manager 43. The status manager 43 is connected to the synchronous controller 44.
In addition, a timing generator 30 is commonly connected to the interfaces 21, 22, a write/read processor 34, a packet read controller 31, and a write controller 33. The write controller 33 is connected to the memory 16, and the write/read processor 34 is connected to the memory 23. A buffer flow controller 32 is connected to the packet read controller 31.
The timing generator 30 provides timing signals for the interfaces 21, 22, the packet read controller 31, the write controller 33, and the write/read processor 34 respectively, and provides the frame pulse 120 or the like for the multi-frame generator 46.
The multi-frame generator 46 generates, based on the frame pulse 120, a multi-frame marker (occasionally referred to as a multi-frame pulse) 116=“1111” and a frame number 117 to generate a TDM multi-frame 113 into which the marker and the frame number are inserted, which is transmitted to the multiplexer 45.
The interfaces 21, 22 each have a built-in speed conversion buffer, which performs a serial conversion of E1, E2 byte data (EOW) respectively on a wireless and a wire circuit side of a parallel signal which is the monitoring control information sent from the OW processor and the DCC processor, and M1-RSDCC, M1-MSDCC byte data respectively on the wireless and the wire circuit side, Mn-RSDCC byte data on the wireless circuit side, and M2-RSDCC-M7-RSDCC byte data on the wire circuit side, which are temporarily stored in the built-in buffer. The byte data are multiplexed into a predetermined position of the TDM multi-frame 113 in the multiplexer 45 based on the timing signals from the timing generator 30.
The memory 23 temporarily stores radio protection switchover control information (an RPS_SW drive signal 103 and a BSW number signal 104) which is the monitoring control information sent from the RPS LGC processor 20. These signals are sent to the multiplexer 45 from the write/read processor 34 based on the timing signals from the timing generator 30, and are multiplexed into the predetermined position of the TDM multi-frame 113.
The packet generator 12 extracts, through the interface 11, only a CPU write signal (see FIG. 11A ({circle around (1)}-{circle around (4)}) which is outputted onto the system bus of the CPU 1 at random for accessing each of the channel portions 50, and extract therefrom an address and data on the system bus of the CPU 1 to be packetized.
The packet buffer 13 stores the packet data divided into packet data amounts transmittable for one period (see FIG. 11B) of the TDM frame. The packet read controller 31 reads the packet data of a single TDM frame from the packet buffer 13 to be multiplexed into a predetermined slot of the TDM frame (see FIG. 11C ({circle around (1)},{circle around (2)}).
It is to be noted that through the packetization by the packet generator 12, a 3-byte write address and 1-byte data are generated as a single packet data 105 that is the monitoring control information (see FIG. 11D).
Also, in the packet buffer 13, 15 pieces of packet data having 1-byte parity check data added thereto are sequentially written in the packet buffers 13_1-13_k as one block data.
Moreover, monitoring the remaining memory capacity of the packet buffer 13 and having found that it has reached a preset threshold value, the packet generator 12 extends the time than usual to return an acknowledge signal DACK to the main CPU through the interface 11. While waiting to receive the signal DACK, the main CPU does not access the channel portions 50. As a result, writing amount in the packet buffer 13 is restricted, thereby preventing the packet buffer 13 from overflowing.
The packet read controller 31 and the buffer flow controller 32 carry out a read control to the 15 packet data (105) CPU_WR1-15 and 1 byte parity data CPU_WR_PRT stored in the packet buffer 13 as 1 block data based on the timing signals from the timing generator 30 and send the same to the multiplexer 45, where the packet data 105 is multiplexed into the predetermined position of a TDM frame 112.
The status manager 43 manages a transmission control status of the channel portions 50 based on a received transmission status signal 98 of each of the channel portions 50, and sends a transmission control signal 106 and a channel number to the synchronous controller 44. The transmission control signal 106 and the channel number are transmitted to the multiplexer 45 at the predetermined timing by the synchronous controller 44 and multiplexed into the predetermined position of the TDM multi-frame 113.
The multiplexer 45 transmits the TDM multi-frame 113, into which the above-mentioned signals sent from the interfaces 21, 22, the memory 23, the packet buffer 13, and the synchronous controller 44 are multiplexed, to the transmission line 110 through the processor 41.
It is to be noted that the signals transmitted from the common portion 10 to each of the channel portions 50 comprise a frame pulse signal 120 and a clock signal besides the above-mentioned TDM multi-frame 113 transmitted to the above-mentioned transmission line 110.
FIG. 12B shows an arrangement of the TDM frame 112 of the signal multiplexed by the multiplexer 45 and outputted therefrom. FIG. 12A shows the frame pulse 120, which is a frame synchronizing pulse of 8 kHz.
The TDM frame 112 comprises a multi-frame marker 116, a frame number 117, status/RPS command signals STP, ST1-ST7, E1ch, E2ch which are EOW signals on the wireless and the wire circuit sides, M1-RSDCC's and M1-MSDCC's which are DCC signals on the wireless and the wire circuit sides, an Mn-RSDCC signal on the wireless circuit side, M2-RSDCC-M7-RSDCC signals on the wire circuit side, one SSMB signal SSMB ({circle around (4)}, two SSMB signals DUMY, 15 CPU write signals CPU_WR1-15 which compose the packet data 105, and data WR-PRY which are parity check data of the packet data 105. Each of them has slots whose number is shown in FIG. 12B with a unit slot being composed of 8 bits.
In addition, one TDM multi-frame 113 is composed of the TDM frame 112 aggregated by 320 frames. When the multi-frame marker 116 is “1111”, indicating the first frame of the multi-frame, “0”-“319” frames are inserted into the slot of the frame number 117 in synchronization with this multi-frame marker 116.
It is to be noted that a guard time slot GT is inserted into a suitable position of the TDM frame 112 in consideration of a wireless data transfer.
FIG. 12C shows an arrangement of the status/RPS command signals STP, ST1-ST7, which comprise the guard time GT of 8 bits, the status of 8 bits, and the RPS command of 16 bits. The status signal comprises the transmission control signal 106 and the channel number, and the RPS command signal comprises the SW number signal 104 and a SW drive command 103.
In the above-mentioned prior art information transfer equipment, means for accommodating CPU bus in communication path for transferring information within the equipment are realized by making bus information of CPU write cycle a predetermined packet for performing a clock change to a writing clock in the channel portions. This clock change of the packet (from CPU clock to synchronous communication path clock) is realized by DP-RAM or the like.
A schematic flow of the CPU access (write operation) is shown in FIG. 13. Firstly, a firmware 1 executes a normal CPU write access processing by designating a monitored address (at step S301). Upon receipt thereof, the common portion 10 packetizes the CPU access data, and makes a completion notification to the firmware 1 in a CPU access completion processing (at step S302).
Moreover, the common portion 10 executes buffering the packet by 8 kHz unit (at step S303), and after receiving a write completion notification (at step S304), executes read processing synchronizing with an SD framing (at step S305), and transfers the packet to the channel portion 50 by a down frame (at step S306).
When writing in a real I/O register 200 is completed (at step S310) by the past CPU access corresponding processing (at step S307), the channel portion 50 confirms the data (or address) of the designated timeslot of the frame transmitted by the above-mentioned step S306. When it is the object packet, a pseudo CPU bus cycle is generated to make the bus accessible (at step S308). Moreover, the writing operation by the bus access is executed (at step S309), and the writing in the real I/O register 200 is executed (at step S311).
In the above-mentioned CPU access (writing operation), the firmware 1 accesses the I/O register of the channel portions, with being completely unconscious of the packetization or of the existence of the DP-RAM (interim buffer), as an access medium equivalent to ordinary general-purpose memory or register. Thus, it is very beneficial to realize an information transfer function within the equipment for making the firmware unconscious of the hardware such as the interim buffer in terms of using the existing firmware. Moreover, the structure of the firmware can be simplified, thereby contributing to shortening the term of equipment developments.
However, in the prior art information transfer equipment, when a certain channel portion is powered ON/OFF or mounted/unmounted from the equipment under the normal-operation state, it has been required that the firmware executes re-setting the system operation information to the channel portion. This system operation information re-setting is a processing of a higher priority than other normal processings, so that when the firmware (CPU system) detects a necessity of the re-setting processing, the normal operation has to be suspended until the predetermined information is derived a work table to be developed to the channel portion.
For such a re-setting processing, a time of approximately 100 msec. is required, which corresponds to 10% of a monitoring polling cycle (generally on the order of 1 sec.) of normal operation. Specifically, in an SDH wireless multiplexer where multi-channelization is noticeable, the simultaneous power ON/OFF of a plurality of channels is not a rare case, so that assuming the worst case of all of the channels, the system processing performance is to extremely decline.
Also, in the prior art information transfer equipment, there are following problems with respect to the operation of the firmware at the time of channel switchover.
Generally, in a wireless equipment, at least one standby channel is prepared in order to prevent the main circuit from entering a non-service state at the time of a circuit failure or an equipment failure, so that upon various failures in the above-mentioned main circuit, a radio protection switching is executed.
On the other hand, with the system being made to have multiple functions, each of the channel portions in the prior art information transfer equipment operates with individually different setting information according to the system setting information.
Therefore, when executing radio line switchover, a system setting change for the standby channel portion is required for the preparation of the switchover. Namely, before switching the SW, the system setting information of the original channel portion is required to be set in the standby channel portion. This processing is executed by the firmware in the prior art information transfer equipment.
In order to complete the switchover within a period as short as possible, it is common to use an interrupt signal for the notification to the firmware. However, by this interrupt processing, the performance of the monitoring control function executed by the firmware in a steady state declines.
FIG. 14 shows an example of a conventional radio protection switchover sequence. For example, SW_ALM issued by a SW39 of a station B assumes a switchover factor, so that an RPS LGC processor 20 of a station A notifies the firmware 1 of an SW switchover request (SWRQ). For the preparation of switchover to the standby channel portion, the firmware 1 executes processing for setting the system setting information having been set in the original channel portion before the switchover. The actual SW switchover of the channel portion is executed after the system setting for the standby channel portion is completed in both of the stations A and B.
As shown by the station A in FIG. 14, the setting change processing of the standby channel portion by the firmware requires a time of several 100 msec. which is longer compared to the time required for the transmission/reception of signals to/from both of the stations A and B or the SW switching processing, thereby accounting for most part of the time before the switchover completion of the radio line switchover sequence.
The time before the switchover completion directly leads to the non-service time (line disconnection time), so that it should be approximated to zero as much as possible. Generally, a time of 50 msec. or less is believed to be a permissive level, but this general requirement has not been fulfilled by the prior art.